Solido Launches PVTMC Verifier from its Machine Learning Labs

Solido Design Automation Inc., the leading provider of machine learning-based variation-aware design and characterization software, today announced the launch of PVTMC Verifier. PVTMC Verifier uses machine learning to thoroughly verify designs across the complete spectrum of process variation and operating conditions, enabling users to reduce their design cycle time, produce more competitive chips, and prevent silicon failures.

For design applications such as automotive, mobile, high-performance computing and Internet of Things (IoT), it has become increasingly necessary to thoroughly verify for variability across all possible operating and process conditions before sending to silicon, to reduce risk of respins or yield loss. Because process variation and operating conditions frequently interact with one another at advanced process nodes, simulating them independently can lead to missed critical interaction effects and failures, which can then go unnoticed before silicon.

PVTMC Verifier overcomes this problem by simulating across the full combinatorial space of process variation and operating conditions together, taking into account interactions between statistical variation and PVTs to ensure that the true worst-case performance conditions are identified.

PVTMC Verifier is more than 100x faster than the equivalent brute force verification, enabling full coverage of all PVT and statistical conditions. The time-to-market reduction, combined with PVTMC Verifier’s ability to pinpoint circuit failure points before going to silicon, results in substantial profitability improvements for design teams.

“PVTMC Verifier is the third product to come out of Solido ML Labs, announced earlier this year,” said Amit Gupta, president & CEO of Solido Design Automation. “We continue to apply our machine learning platform technologies and years of expertise to customer problems that are not addressable using brute-force solutions.”

With PVTMC Verifier, development teams can bring more competitive and successful designs to market, with less silicon iteration, reduced die area, and lower engineering and manufacturing costs.


PVTMC Verifier is available immediately in the Solido Variation Designer product line, and has been rolled out to Solido’s user base spanning over 2000 analog/RF, I/O,…

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