Arasan Chip Systems Announces Industry’s First MIPI C-PHY HDK

Arasan’s HDK offers the fastest and surest path for companies looking to adopt the latest MIPI standards.

Arasan, a leading provider of IP for semiconductor design and manufacturing, today announced availability of its MIPI C-PHYSM HDK built using an Arasan C-PHY IC. The HDK supports C-PHY v1.1 with speeds of up to 2.5GHz and D-PHY v1.2 also with speeds of up to 2.5GHz.

Arasan’s HDK offers the fastest and surest path for companies looking to adopt the latest MIPI standards. The HDK is part of Arasan’s Total IP Solution for MIPI.

This HDK enables customers to prototype their C-PHY based projects using Arasan’s MIPI DSI or CSI IP Cores and software stacks. The HDK can be easily integrated with Xilinx based FPGA platforms using a FMC Connector. After prototyping, the entire design can be licensed including the MIPI C- PHY / D-PHY combo IP GDS II, MIPI CSI or DSI Verilog RTL and firmware.

Arasan’s C-PHY IP has been adopted extensively by automobile, drone and imaging SoC manufacturers. Arasan is a TSMC OIP partner supporting physical interface IP for MIPI, JEDEC, ONFI, USB and SD. The C-PHY HDK board will be assembled with either a C-PHY TSMC 28nm or TSMC 12nm ASIC.


Arasan CPHY HDK is available for immediate sale. Due to high demand, the lead time for delivery is 4-6 weeks from order date with a minimum order quantity of 12 boards. Please contact Sales “at” for additional information.


Arasan will host a free live webinar on MIPI C-PHY HDK and IP webinar to show the workings of our HDK and overview of our CPHY IP. Please check the website for registration information:


MIPI C-PHY is an embedded clock link that provides extreme flexibility to reallocate lanes within a link. It also offers low latency transitions between high speed and low power modes. MIPI C-PHY accomplishes this by departing from a conventional differential signaling technique on two-wire lanes and introducing three-phase symbol encoding of about 2.28 bits/symbol to transmit data symbols on three-wire lanes, or “trios”, where each trio includes an embedded clock. Three trios operating at 3.5 GSym/s achieve a peak data rate of about 24 Gbps over a nine-wire interface. MIPI…

Read the full article from the Source…

Leave a Reply

Your email address will not be published. Required fields are marked *